Regviz

Microchip Technology /ATSAMS70Q20B /USBHS /HSTPIPICR_ISO_MODE[3]

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as HSTPIPICR_ISO_MODE[3]

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/Microchip Technology/ATSAME70N20B/USBHS/HSTPIPICR_ISO_MODE[3]#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (RXINIC)RXINIC 0 (TXOUTIC)TXOUTIC 0 (UNDERFIC)UNDERFIC 0 (NAKEDIC)NAKEDIC 0 (OVERFIC)OVERFIC 0 (CRCERRIC)CRCERRIC 0 (SHORTPACKETIC)SHORTPACKETIC

Description

Host Pipe Clear Register

Fields

RXINIC

Received IN Data Interrupt Clear
TXOUTIC

Transmitted OUT Data Interrupt Clear
UNDERFIC

Underflow Interrupt Clear
NAKEDIC

NAKed Interrupt Clear
OVERFIC

Overflow Interrupt Clear
CRCERRIC

CRC Error Interrupt Clear
SHORTPACKETIC

Short Packet Interrupt Clear

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data